Overview

Virtual Memory is a hardware-software abstraction co-designed by the Operating System kernel and the CPU’s Memory Management Unit (MMU). It presents each application process with the illusion of a contiguous, private block of physical memory (the Virtual Address Space), while secretly scattering, sharing, and paging actual data across non-contiguous physical DRAM frames and secondary persistent disk storage.

Module Notes

Architecture Overview of Virtual Memory

Core Objectives & Guarantees

1. Memory Protection & Isolation: Processes cannot read or write to memory belonging to other processes or the kernel without explicit permission. A bug or exploit in Process A cannot corrupt Process B.
2. Transparency: Applications execute as if they have access to a large, contiguous memory space starting at address 0x0, completely oblivious to the physical RAM configuration or competing processes.
3. Efficiency & Flexibility: Physical RAM can be fragmented across non-contiguous frames. Infrequently accessed data can be transparently swapped out to disk via Demand Paging without altering process execution.

Dual-Address Space Paradigm

In a virtual memory architecture, two distinct address realms exist simultaneously:

graph LR
    subgraph Process1 ["Process 1 Virtual View"]
        P1_VA["Contiguous Virtual Address Space<br/>0x00000000 -> 0x7FFFFFFF"]
    end

    subgraph Process2 ["Process 2 Virtual View"]
        P2_VA["Contiguous Virtual Address Space<br/>0x00000000 -> 0x7FFFFFFF"]
    end

    subgraph MMU_Layer ["Hardware Indirection (MMU)"]
        PT1["Process 1 Page Table"]
        PT2["Process 2 Page Table"]
    end

    subgraph PhysicalRAM ["Actual Hardware RAM"]
        RAM1["Frame 12 (P1 Code)"]
        RAM2["Frame 45 (P2 Code)"]
        RAM3["Frame 88 (P1 Heap)"]
        RAM4["Frame 102 (Shared Lib)"]
    end

    P1_VA --> PT1
    P2_VA --> PT2
    PT1 --> RAM1
    PT1 --> RAM3
    PT1 --> RAM4
    PT2 --> RAM2
    PT2 --> RAM4

• Virtual Address (VA): An address generated by the CPU during instruction fetch/execution (e.g., mov rax, [rbx]). Every application operates strictly with Virtual Addresses.
• Physical Address (PA): The actual hardware bus signal addressing physical DRAM chips. Physical RAM is managed in fixed-size blocks called Page Frames.

The Address Translation Pipeline

Whenever a process issues a memory reference, hardware intercepts and translates the address before accessing physical RAM:

flowchart TD
    CPU["CPU executes instruction referencing VA"] --> MMU["MMU Intercepts Virtual Address"]
    MMU --> QueryTLB{"Check Translation Lookaside<br/>Buffer (TLB) Cache"}
    
    QueryTLB -->|"TLB Hit (Fast)"| PA_Calc["Combine Physical Frame Number (PFN)<br/>+ Address Offset"]
    QueryTLB -->|"TLB Miss (Slow)"| Walk["Walk Hierarchical Page Table Tree in RAM"]
    
    Walk --> CheckPTE{"Inspect Page Table Entry (PTE)"}
    CheckPTE -->|"Present Bit = 0"| Trap["Raise Hardware Exception:<br/>Page Fault Trap"]
    CheckPTE -->|"Protection Bit Violation"| Segfault["Raise Hardware Exception:<br/>Access Violation (SIGSEGV)"]
    CheckPTE -->|"Valid & Present"| CacheTLB["Load PTE into TLB"]
    CacheTLB --> PA_Calc
    
    PA_Calc --> RAM["Read/Write Physical DRAM Address"]
    Trap --> OS_Handler["OS Kernel Page Fault Handler<br/>(Load Page from Disk Swap)"]

User/Kernel Virtual Address Space Split

Modern operating systems map both user application memory and kernel memory into every process’s single virtual address space to eliminate the need to switch entire page tables during a system call.

• User Space: Accessible in both User Mode and Kernel Mode. Holds user executable code, stack, heap, and dynamic libraries.
• Kernel Space: Accessible only when CPU executes in Kernel Mode (Ring 0). Contains kernel data structures, device drivers, and page tables. Protected by hardware supervisor flags in the Page Table Entry.

Advanced Capabilities Enabled by Virtual Memory

Because virtual addresses are decoupled from physical storage, operating systems leverage this indirection for zero-copy performance features:

1. Copy-on-Write (CoW): When a process forks, child and parent share identical physical pages marked read-only. Pages are replicated only when one process attempts a write operation.
2. Memory-Mapped Files (mmap): Maps persistent files directly into a process’s virtual memory address space, substituting disk I/O calls (read/write) with fast memory access.
3. Shared Memory (shm_open): Maps the exact same physical DRAM frames into the virtual address spaces of two distinct processes, enabling ultra-fast Inter-Process Communication (IPC).

Related Modules

• Paging
• Translation Lookaside Buffer (TLB)
• Demand Paging & Page Faults
• Dual-Mode Operation & Memory Protection
• Memory Management Directory