CPU Control and Datapath Execute Instruction Set
Control takes program as input, it interprets each instruction and tell the Datapath to operate on data via ALU, memory and registers
CPU Components ― Single Cycle Execution
Assumptions
- Every machine language instruction happens in clock cycle
- MIPS architecture (Microprocessor without interlocked pipeline stages)
- reg-reg architecture: all operands must be in registers (total 24)
- 3 Instruction Types:
- R-Type: all data in registers (mostly arithmetic and logical operations)
- I-type: branches, memory transfers, constants
- J-type: jumps and calls
R-type Instructions: Register to Register ALU ops
OPCODE: tells operation to be performedRS: Source Register 1 (attached to “read register 1” input)RT: Source Register 2 (attached to “read register 2” input)RD: Destination Register (attached to “write register” input)shamt: Shift Amount for shift operationsFUNCT: Tells specific variant of operation (eg. add/sub have same opcode)
Steps for R-Type Instruction Operations
Step 1. Fetch instruction and advance PC
Step 2. Read two registers and set control signals
Step 3. Perform the ALU operation
Step 4: Write result to register
I-Type: Store Instruction
OPCODE: Tells operation to be performedRS: Base Address Register (attached to “read regester 1” input)RT: Source register whose value will be stored to memory (attached to “read register 2” input)OFFSET: Constant offset (added to the base address inRS)
Steps for I-Type (Store) Instruction Operations
Step 1: Fetch instruction and advance PC
Step 2 (store): Read register values and set control signals
Step 3 (store): Compute the Address
Step 4 (store): Write the value to memory
I-Type: Conditional Branch
RS: Source Register 1 (attached to “read register 1” input)RT: Source Register 2 (attached to “read register 2” input)BRANCH TARGET'S OFFSET: Word offset, which we multiply by 4 (via << 2) to get Bit Offset, then add to PC+4 to get the address of the instruction to which we branch ifRS == RT(PC-relative address)
Steps for I-Type (Conditional) Instruction Operations
Step 1 (beq): Fetch instruction and advance PC
Step 2 (beq): Read register values and set control signals
Step 3 (beq): Compare registers, calculate branch target, and choose new PC
J-Type: Unconditional Branch
BRANCH TARGET ADDRESS: Actual Address (in words) which we multiply by 4 (<< 2) to get 28-bit address, then concatenate to upper 4 bits of PC+4 to get the 32 bit address of instruction to which we branch unconditionally
