Mux, Demux

Abstract

Multiplexers (Muxes) and Demultiplexers (Demuxes) are the foundational data-steering components of digital architecture. Built from Transmission Gates and Tristate Buffers (which enable high-impedance $Z$ floating states for shared bus communication), a multiplexer selects one of $N=2^n$ data inputs to route to a single output based on $n$ select control lines. Beyond data steering, $2^n:1$ multiplexers function as universal logic generators. Conversely, a demultiplexer directs a single input signal to one of $2^n$ outputs governed by control select inputs and enable signals.

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Physical Building Blocks: Transmission Gates & Tristate Buffers

Transmission Gate Switches

Because standalone nMOS switches pass $1$s poorly and standalone pMOS switches pass $0$s poorly, Transmission Gates (TGs) combine nMOS and pMOS transistors in parallel to pass full-rail $0$s and $1$s efficiently:

• When $EN=1$ ($E{N}^{\prime }=0$): Switch is ON. Input $A$ is connected directly to output $B$.
• When $EN=0$ ($E{N}^{\prime }=1$): Switch is OFF. Input $A$ is disconnected from $B$.

Tristate Buffers & Shared Busses

When a switch is OFF, the output node enters a High-Impedance ($Z$) / Floating / Open state.

Floating nodes allow multiple distinct drivers to connect to a single Tristate Bus, provided that exactly one driver is active ($E=1$) at any given time.

Tristate Buffer Symbol and Bus Architecture

Tristate Buffer Truth Table

Enable ($E$)	Input ($A$)	Output ($Y$)	State Description
$0$	$0$	$Z$	High Impedance (Disconnected)
$0$	$1$	$Z$	High Impedance (Disconnected)
$1$	$0$	$0$	Driven Low
$1$	$1$	$1$	Driven High

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Multiplexers (Mux)

A Multiplexer selects one of $N$ data inputs and routes it to a single output using $n={\log }_{2}N$ select control lines.

2:1 Multiplexer Block Diagram and Internal Logic

2:1 Multiplexer

• Inputs: Data $D_0,D_1$, Select $S$
• Boolean Equation: $Z=S^{\prime }{D}_0+S{D}_1$

2:1 Mux Truth Table & State Mapping

Select ($S$)	Input $D_0$	Input $D_1$	Output ($Y$)
$0$	$0$	$X$	$0$
$0$	$1$	$X$	$1$
$1$	$X$	$0$	$0$
$1$	$X$	$1$	$1$

$$\text{Compact Function: }Y=\{\begin{array}{ll}{D}_0& \text{if }S=0\\ D_1& \text{if }S=1\end{array}$$

General $2^n:1$ Multiplexer Equations

For a $2^n:1$ Mux with $n$ select lines, the output is the sum of products of each minterm $m_k$ (formed by the select lines) and its corresponding data input $I_k$:

$$Z=\sum _{k=0}^{2^n-1}{m}_k{I}_k$$

General Minterm-based Multiplexer Structure

4:1 Multiplexer ($n=2$, Selects $A,B$)

$$Z=A^{\prime }{B}^{\prime }{I}_0+A^{\prime }B{I}_1+A{B}^{\prime }{I}_2+AB{I}_3$$

8:1 Multiplexer ($n=3$, Selects $A,B,C$)

$$Z=A^{\prime }{B}^{\prime }{C}^{\prime }{I}_0+A^{\prime }{B}^{\prime }C{I}_1+A^{\prime }B{C}^{\prime }{I}_2+A^{\prime }BC{I}_3+A{B}^{\prime }{C}^{\prime }{I}_4+A{B}^{\prime }C{I}_5+AB{C}^{\prime }{I}_6+ABC{I}_7$$

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Multiplexers as General-Purpose Logic Generators

A $2^n:1$ Mux can implement any $(n+1)$-variable Boolean function by connecting $n$ variables to the select lines and driving the data inputs $I_k$ with $0$, $1$, or the remaining variable (and its complement).

Example Design Problem

Implement the 3-variable function $Z(A,B,C)=AC+B{C}^{\prime }+A^{\prime }{B}^{\prime }C$ using a 4:1 Multiplexer (Select lines connected to $A,B$).

Method 1: Plug-and-Chug (Algebraic Evaluation)

Evaluate $Z(A,B,C)$ for each fixed combination of select variables $(A,B)$:

$$\begin{array}{rl}\text{For }(A,B)=(0,0):Z(0,0,C)& =(0)C+(0)C^{\prime }+(1)(1)C=C⟹{\mathbf{I}}_0=\mathbf{C}\\ \text{For }(A,B)=(0,1):Z(0,1,C)& =(0)C+(1)C^{\prime }+(1)(0)C=C^{\prime }⟹{\mathbf{I}}_1={\mathbf{C}}^{\prime }\\ \text{For }(A,B)=(1,0):Z(1,0,C)& =(1)C+(0)C^{\prime }+(0)(1)C=C⟹{\mathbf{I}}_2=\mathbf{C}\\ \text{For }(A,B)=(1,1):Z(1,1,C)& =(1)C+(1)C^{\prime }+(0)(0)C=C+C^{\prime }=1⟹{\mathbf{I}}_3=1\end{array}$$

Method 2: K-Map Partitioning

Partition the 3-variable K-Map into sub-blocks corresponding to select states $AB\in \{00,01,10,11\}$ and identify the output relationship relative to variable $C$:

K-Map Partitioning for Mux Data Input Derivation

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Demultiplexers (Demux)

A Demultiplexer performs the inverse operation of a multiplexer: it routes a single data input line $X$ to one of $2^n$ output lines $Y_i$, selected by $n$ control lines $(S_{n-1},\dots ,S_0)$.

1-to-N Demultiplexer Logic Diagram

Mathematical Function Definition

$$Y_i=\{\begin{array}{ll}X& \text{if }i=(S_{n-1},\dots ,S_0{)}_2\text{ and }EN=1\\ 0& \text{otherwise}\end{array}$$

Enable Line Behavior

If the enable line $EN=0$, all outputs $Y_i$ remain forced to $0$, regardless of input $X$ or select line values.

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Related Notes

• Logic Functions
• Adders & Subtractors
• Comparator
• Arithmetic Logic Unit Integration
• Arithmetic Logic Units