Non-Volatile Memory (NVM)

Abstract

Non-Volatile Memory (NVM) retains binary data indefinitely when system power is removed. Traditional NVMs (EPROM, EEPROM, Flash) rely on floating-gate charge trapping. Emerging NVM technologies (FeRAM, STT-RAM/MRAM, PCM, FeFET, and ReRAM) represent a maturing class of solid-state storage that bridges the boundary between fast, volatile working memory (SRAM/DRAM) and slow, non-volatile mass storage (Flash/SSD). Offering near-SRAM access speeds, DRAM-like density, and high energy efficiency, emerging NVMs target big data analytics and persistent in-memory computing architectures.

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Traditional Non-Volatile Memory Evolution

Traditional Read-Only Memory (ROM) devices evolved from factory-programmed circuits into in-system programmable non-volatile storage.

Floating-Gate Transistor Mechanics

Traditional floating-gate transistors embed an electrically isolated gate inside an oxide layer. High programming voltages force electrons to tunnel into the floating gate, trapping them to shift the transistor’s threshold voltage ($V_T$) to store logic '0'.

flowchart LR
    subgraph Layer["Device Layer"]
        direction TB
        CG["Control Gate"]
        FG["Floating Gate"]
        SUB["Substrate"]
    end

    subgraph Function["State / Operation"]
        direction TB
        V["Applied Programming Voltage"]
        E["Trapped Electrons (Logic '0')"]
        CH["Source/Drain Channel"]
    end

    CG -->|Drives| V
    FG -->|Stores| E
    SUB -->|Conducts| CH

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Evolutionary ROM Spectrum

Erasable Programmable ROM (EPROM):

Programmed using higher voltages to trap electrons in floating gates. Erased by exposing the chip to ultraviolet (UV) light through a quartz package window to energize trapped electrons.

Electrically-Erasable Programmable ROM (EEPROM):

Injects and erases electrons electronically at byte/word granularity without requiring UV exposure.

Flash Memory: Operates on principles similar to EEPROM, but optimizes erasure density by erasing large blocks of words simultaneously. Both EEPROM and Flash are In-System Programmable (ISP).

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Emerging NVM Paradigm

Emerging NVM technologies blur the historical distinction between Memory (fast, expensive, volatile) and Storage (slow, cheap, non-volatile).

flowchart TD
    subgraph Traditional["Traditional Memory Limitations"]
        SRAM["<b>SRAM</b><br/>Fast Read/Write<br/>Low Density (6T Cell)<br/>Volatile"]
        DRAM["<b>DRAM</b><br/>High Density (1T1C)<br/> Requires Power Refresh<br/> Volatile"]
        Flash["<b>NAND Flash</b><br/>Non-Volatile (~10 Yrs)<br/> High Write Latency<br/> Limited Endurance"]
    end

    subgraph SweetSpot["<b>Emerging NVM Sweet Spot</b><br/>(Storage-Class / Universal Memory)"]
        direction TB
        NV["<b>Non-Volatile</b><br/>10+ Year Retention"]
        SP["<b>SRAM Speed</b><br/>Nanosecond Read/Write"]
        DN["<b>DRAM Density</b><br/>1T1R / 3D Cross-Point"]
    end

    SRAM -->|Provides Speed| SP
    DRAM -->|Provides Density| DN
    Flash -->|Provides Retention| NV

Key Technical Features & Challenges

• Target Applications: Excellent fit for Big Data analytics (in-memory databases) and energy-efficient edge AI processing by eliminating static leakage and refresh power.
• Maturing Challenges:
  • Slow Writes: Write operations require higher current or longer pulse durations than reads.
  • Write Endurance: Cell degradation under repeated switching cycles ($10^5\dots 10^7$ cycles for PCM/ReRAM).
  • Manufacturing Complexity: Requires integrating novel ferroelectric, phase-change, or magnetic materials onto standard CMOS back-end processes.

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Emerging NVM Technology Breakdown

1. Ferroelectric RAM (1T-1C FeRAM)

• Mechanics: Similar to DRAM (1 Transistor, 1 Capacitor), but replaces the dielectric with a ferroelectric layer (typically Lead Zirconate Titanate - PZT). Electric fields shift central atoms into up/down polarization states representing '1' or '0'.
• Advantages: $99\%$ lower power than DRAM; no refresh cycles required; fast read/write performance.
• Disadvantages: Destructive reads require rewriting data after every read cycle; physical scaling limits below $130\text{ nm}$ as materials lose ferroelectricity.

1T-1C FeRAM Cell Structure

2. Spin-Transfer Torque RAM (STT-RAM / MRAM)

• Mechanics: Stores data using a Magnetic Tunneling Junction (MTJ) with a Fixed Magnetic Layer and a Free Magnetic Layer. Spin-polarized electron currents align free-layer magnetization parallel (P = '1', low resistance) or anti-parallel (AP = '0', high resistance) to the fixed layer.
• Advantages: High endurance ($10^6\dots 10^{12}$ cycles); ultra-fast read latency ($\sim 10\text{ ns}$); high retention ($\ge 10\text{ years}$).
• Disadvantages: Asymmetric write energy: Writing a '1' requires significantly higher current and duration than writing a '0'.

STT-RAM Magnetic Tunneling Junction (MTJ) Structure

3. Phase Change Memory (PCM / PCRAM)

• Mechanics: Thermally shifts a chalcogenide material between an amorphous phase (RESET, high resistance) and a crystalline phase (SET, low resistance) via electrical current pulses.
• Advantages: Excellent physical cell scalability beyond other emerging NVMs.
• Disadvantages: Slow write times; limited write endurance ($10^7$ cycles); high write power.

PCM Crystalline (SET) vs. Amorphous (RESET) States

4. Ferroelectric Field-Effect Transistor (1T FeFET)

• Mechanics: Integrates ferroelectric material directly into the gate stack of a single FET transistor. Reversible threshold voltage ($V_T$) shifts are driven by sub-$|5\text{V}|$ nanosecond field pulses.
• Advantages: Non-destructive read detection; co-located directly with CMOS logic gates (requiring only $2\text{–}4$ additional mask layers).

1T FeFET Co-Located Logic Transistor Cell

5. Resistive RAM (ReRAM)

Stores data by forming (low resistance) or breaking (high resistance) conductive atomic filaments across a dielectric oxide layer using applied voltage pulses.

• Access-Based ReRAM (1T-1R): Pairs 1 Transistor with 1 Resistor. Offers ultra-fast reads/writes ($\approx 20\text{ ns}$), low latency ($10^{-8}\text{ s}$), but lower capacity. Serves as an alternative to embedded NOR flash.
• Crossbar ReRAM (1T-nR): Organizes cells at perpendicular wire intersections in dense 3D arrays. Highly scalable and cheap, providing an alternative to NAND flash and SSD disk caches.

1T-1R Access ReRAM vs. 1T-nR 3D Crossbar Architecture

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Quantitative Technology Comparison Matrix

Emerging NVM Technology Comparison

Metric	MRAM	ReRAM	eFlash	FeRAM
Non-Volatility	Yes ($\ge 10\text{ yrs}$)	Yes ($\sim 10\text{ yrs}$)	Yes ($\sim 10\text{ yrs}$)	Yes ($\ge 10\text{ yrs}$)
Read Latency	$\sim 10\text{ ns}$	$\sim 10\text{ ns}$	$\sim 60\text{ ns}$	$\sim 20\text{ ns}$
Write Latency	$20\text{–}100\text{ ns}$	$10\text{–}50\text{ ns}$	$10\text{–}100\mu \text{s}$	$20\text{ ns}$
Write Voltage	$1.8\text{ V}$	$3\text{ V}$	$3\text{ V}$	$0.6\text{ V}$
Endurance (Cycles)	$10^6\text{–}10^{12}$	$\sim 10^5$	$10^4\text{–}10^5$	$10^{12}\text{–}10^{15}$
Multi-Level Cell	Limited ($1\text{-bit}$)	Good	Good	Limited ($1\text{-bit}$)
Scalability	Good ($\le 22\text{ nm}$)	Good	Limited	Limited
Reliability	High	Limited	High (Low endurance)	High

NVM Quantitative Metric Comparison Chart

Full Memory Spectrum Feature Comparison

Feature	SRAM	eDRAM	STT-RAM	PCRAM	ReRAM
Density	Low	High	High	Very High	Very High
Speed	Very Fast	Fast	Fast Read / Slow Write	Slow Read / Very Slow Write	Slow Read/Write
Dynamic Power	Low	Medium	Low	Low	Low
Leakage Power	High	Medium	Low	Low	Low
Non-Volatility	No	No	Yes	Yes	Yes

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System Architecture Replacement Mappings

Emerging NVM technologies target specific replacements across the memory hierarchy:

flowchart LR
    subgraph Traditional["<b>Traditional Volatile / Flash Memory</b>"]
        direction TB
        T1["L1/L2/L3 Caches<br/>(SRAM)"]
        T2["Main Memory<br/>(DRAM)"]
        T3["Flash / Storage<br/>(NAND)"]
    end

    subgraph Emerging["<b>Emerging Non-Volatile Replacement</b>"]
        direction TB
        E1["STT-RAM<br/>(Eliminates Static Leakage Power)"]
        E2["PCRAM<br/>(High Density Non-Volatile RAM)"]
        E3["ReRAM<br/>(3D Crossbar / High Throughput)"]
    end

    T1 -->|Replace with| E1
    T2 -->|Replace with| E2
    T3 -->|Replace with| E3

1. STT-RAM $\to$ SRAM Cache Replacement: Eliminates static leakage power in dense multi-core CPU caches.
2. PCRAM $\to$ DRAM Main Memory Replacement: Provides high-density, non-volatile main memory arrays for persistent in-memory database systems.
3. ReRAM $\to$ NAND / NOR Flash Replacement: 1T-1R access ReRAM targets embedded NOR replacement for Execute-in-Place (XiP) code, while 3D Crossbar ReRAM replaces NAND flash in data center block storage.

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Related Notes

• Memory Hierarchy
• Cache Design
• Memory Types
• Memory