Overview
Digital Systems forms the architectural bridge between physical semiconductor transistors and programmable, general-purpose computing processors. This directory organizes digital design principles into a 6-layer modular hierarchy: foundational Number Representation & Logic Gates, Boolean optimization in Logic Design, combinational operators in Arithmetic Logic Units (ALUs), state storage in Sequential Circuits, high-level system partitioning in RTL Design, and high-density Memory Subsystems—culminating in complete CPU Design.
System Abstraction Roadmap
flowchart TD Layer1["<b>1. Number Rep. & Basic Gates</b><br>Transistors, Boolean Algebra & Number Systems"] --> Layer2["<b>2. Logic Design</b><br>K-Maps, Canonical Forms & Logic Minimization"] Layer2 --> Layer3["<b>3. Arithmetic Logic Units (ALUs)</b><br>Adders, Muxes, Shifters & Comparators"] Layer3 --> Layer4["<b>4. Sequential Circuits</b><br>Flip-Flops, Registers, Counters & FSMs"] Layer4 --> Layer5["<b>5. RTL Design</b><br>HLSMs, Datapath/Control Partitioning & Synthesis"] Layer5 --> Layer6["<b>6. Memory Subsystems</b><br>Cache Design, Memory Hierarchy & NVM"] Layer3 --> CPU["<b>7. CPU Design</b><br>Instruction Execution, Control Units & Datapath Integration"] Layer4 --> CPU Layer5 --> CPU Layer6 --> CPU
Directory Structure & Submodule Index
| Module / Directory | Focus & Hardware Scope | Key Topics & Sub-Files |
|---|---|---|
| 1. Number Rep. & Logic Gates | Binary primitives and CMOS gate physics. | Number Systems, Two’s Complement, CMOS Transistors, Logic Gates. |
| 2. Logic Design | Boolean optimization and minimization. | Logic Functions, Canonical SOP/POS, Logic Simplification with K-Maps. |
| 3. Arithmetic Logic Unit (ALU) | Combinational data processing elements. | Adders/Subtractors, Multipliers, Shifters, Mux/Demux, Encoders, ALUs. |
| 4. Sequential Circuits | Clocked storage, counters, and FSMs. | Latches/Flip-Flops, Registers/Counters, FSMs, Setup/Hold Timing Analysis. |
| 5. RTL Design | High-level synthesis and datapath control. | High-Level State Machines (HLSM), 4-Step Synthesis, FIR Filters. |
| 6. Memory Subsystems | Storage cell arrays and cache hierarchies. | Memory Hierarchy, Cache Design (AMAT), SRAM (6T), DRAM, Emerging NVM. |
| 7. CPU Design | Full processor integration and execution. | Datapath, Control Unit, Instruction Fetch/Decode/Execute, Pipelining. |
Submodule Roadmaps
1. Number Representation & Basic Logic Gates
- Number Systems and Boolean Algebra — Positional notation, Two’s complement representation, and Boolean theorems.
- Transistors & Gates — N-Type/P-Type MOSFET switch models, CMOS inverter gates, and logic gate topologies.
2. Logic Design
- Logic Functions — Truth tables, minterms, maxterms, and functional completeness.
- Canonical Representation — Sum-of-Products (SOP) and Product-of-Sums (POS) standard expressions.
- Logic Simplification with K-maps — Karnaugh Map minimization, implicants, essential prime implicants, and Don’t Care () conditions.
3. Arithmetic Logic Units (ALUs)
- Adders & Subtractors — Half adders, full adders, ripple-carry adders, and carry-lookahead adders.
- Multiplier & Divider — Array multipliers, sequential shift-and-add multipliers, and divider circuits.
- Shifters — Logical shifters, arithmetic shifters, rotators, and barrel shifters.
- Mux & Demux — Multiplexers as universal logic generators and demultiplexer routing.
- Encoder & Decoder — Binary decoders, priority encoders, and enable logic.
- Comparator — Magnitude comparators () for multi-bit words.
- Arithmetic Logic Unit — Multi-function ALU integration combining arithmetic, logic, and status flag flags.
4. Sequential Circuits
- Latches & Flip-Flops — SR latches, D latches, master-slave D flip-flops, and edge-triggering.
- Registers and Counters — Parallel registers, shift registers, universal shift registers, and modulo state counters.
- Finite State Machines — State transition diagrams, state tables, Mealy vs. Moore machines, and 5-step FSM synthesis.
- Timing Constraints in Sequential Designs — Contamination/propagation delays, setup/hold constraints, and clock skew ().
5. Register Transfer Level (RTL) Design
- High Level State Machines — Behavioral state modeling, multi-bit local variable storage, and arithmetic conditions.
- RTL Design Process — Step-by-step conversion of HLSMs into Datapath + Controller hardware, and High-Level Synthesis (C to gates).
- Data-Dominant RTL Design & FIR Filters — Data-dominant vs. control-dominant trade-offs, Finite Impulse Response (FIR) filter design, and logarithmic adder trees.
6. Memory Subsystems
- Memory Hierarchy — Latency pyramids, access trade-offs (speed, low power, predictability), and ARMv8 Tightly Coupled Memory (TCM).
- Cache Design — Mapping policies (Direct-Mapped, Set-Associative), replacement rules (LRU), write policies, and AMAT equations.
- Memory Types — array organization, composition expansion (wider words / more words), and cell structures (46T Register File, 6T SRAM, 1T1C DRAM).
- Non-Volatile Memory (NVM) — Floating-gate ROM/Flash evolution and emerging NVM technologies (FeRAM, STT-RAM/MRAM, PCM, FeFET, ReRAM).
7. Core Standalone Module: CPU Design
- Integration of the datapath, control unit, register file, and memory interface to realize an instruction set architecture (ISA) execution pipeline.