Memory Systems

Overview

Memory Systems provide large-scale bit storage organized into addressable multi-bit words across digital computing platforms. The Computer Systems/Digital Systems/Memory/ directory structures memory principles into four core submodules: balancing architectural trade-offs in the Memory Hierarchy, optimizing hit rates via Cache Design, analyzing physical cell structures across Memory Types (ROM vs. RAM), and surveying Emerging Non-Volatile Memory (NVM) architectures.

Directory Structure & Summary Framework

flowchart TD
    Index["<b>Memory Systems Index</b>"]
    
    Index --> Sec1["<b>1. Memory Hierarchy</b><br>Speed, Low Power, Predictability"]
    Index --> Sec2["<b>2. Cache Design</b><br>Mapping, Replacement & Write Policies"]
    Index --> Sec3["<b>3. Memory Types</b><br>ROM vs RAM vs NVM & Cell Mechanics"]
    Index --> Sec4["<b>4. Non-Volatile Memory (NVM)</b><br>Emerging Tech, Big Data & Low Power"]

Submodule Summaries

1. Memory Hierarchy

• Core Focus: Balancing system needs around speed, low power consumption, and predictability.
• Key Topics: Multi-level latency pyramids (Cycles: Cache $1\text{–}30$, DRAM $100\text{–}300$, SSD $25\text{k}\text{–}2\text{M}$), density vs. access cost trade-offs, ARMv8 memory subsystem, and Tightly Coupled Memory (TCM) for deterministic real-time execution.

2. Cache Design

• Core Focus: Structural cache organization, address mapping mechanics, and performance modeling.
• Key Topics: Address mapping strategies (Direct-Mapped, $N$-Way Set Associative, Fully Associative), line replacement policies (LRU, FIFO, Random), write policies (Write-Through vs. Write-Back, Write-Allocate), and Average Memory Access Time (AMAT) equations.

3. Memory Types

• Core Focus: $m\times n$ array organization, composition expansion rules, and physical RAM storage cells.
• Key Topics: $k={\log }_{2}m$ addressing math, bit-width expansion (wider words) and address depth expansion (more words via decoders), square RAM grid layout, and transistor-level mechanics across Register Files ($\approx 46\text{T}$), SRAM ($6\text{T}$), and DRAM ($1\text{T}1\text{C}$ refresh).

4. Non-Volatile Memory (NVM)

• Core Focus: Traditional floating-gate ROM/Flash and maturing Emerging NVM technologies targeting big data and energy-efficient architectures.
• Key Topics: Evolutionary ROM spectrum (EPROM, EEPROM, Flash), emerging NVM technologies (FeRAM 1T-1C, STT-RAM/MRAM MTJ, PCM, 1T FeFET, ReRAM 1T-1R / 3D Crossbar), quantitative comparison matrices, and cache/DRAM/Flash replacement mappings.

Related Directories

• Register Transfer Level (RTL) Design
• Sequential Circuits
• Arithmetic Logic Units (ALUs)
• Digital Systems
• Computer Systems