Arithmetic Logic Unit (ALU) Integration

Abstract

An Arithmetic Logic Unit (ALU) is the central combinational processing core of a CPU processor, executing arithmetic operations (addition, subtraction) and logical operations (bitwise AND, OR) on multi-bit operands. Modern processor architectures—such as MIPS or RISC-V—construct wide $N$-bit ALUs hierarchically by cascading $N$ identical 1-bit ALU primitives. Operating in parallel for bitwise logic and in series for carry propagation, a centralized ALUop control line selects which operation output passes through a multiplexer to the final result bus.

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Top-Level ALU Interface & Signals

At the system level (e.g., MIPS architecture), the ALU accepts two multi-bit data inputs ($A$ and $B$), a multi-bit control opcode (ALUop or Operation), and outputs the computed result along with status flag signals.

Top-Level MIPS-Style ALU Block Symbol

Port Description

• Data Inputs ($A,B$): $N$-bit operands supplied from processor registers or immediate values.
• Operation Select (ALUop): $k$-bit control code generated by the CPU Control Unit indicating the exact operation to execute.
• Output Result: $N$-bit computed output value.
• Status Flags: Optional outputs indicating hardware conditions (e.g., $Zero$, $Overflow$, $CarryOut$).

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1-Bit ALU Building Block

A multi-bit ALU is built by designing a single-bit slice capable of operating on 1-bit inputs $a_i$ and $b_i$.

Internal Components of a 1-Bit Slice

1. AND Gate: Computes bitwise $a_i\cdot b_i$.
2. OR Gate: Computes bitwise $a_i+b_i$.
3. Full Adder: Computes arithmetic sum $a_i+b_i+CarryI{n}_i$, producing $Su{m}_i$ and $CarryOu{t}_i$.
4. Operation Multiplexer: A 3:1 (or 4:1) multiplexer controlled by ALUop to route the desired operation to the output.

Internal Logic Schematic of a 1-Bit ALU Cell

1-Bit ALU Control Decoding Table

ALUop Code	Selected Multiplexer Input	Executed Operation	Output Function ($Resul{t}_i$)
00	Input 0	Bitwise AND	$Resul{t}_i=a_i\cdot b_i$
01	Input 1	Bitwise OR	$Resul{t}_i=a_i+b_i$
10	Input 2	Addition (ADD)	$Resul{t}_i=a_i\oplus b_i\oplus CarryI{n}_i$

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Constructing a 32-Bit Modular ALU Architecture

To process 32-bit operands, 32 individual 1-bit ALUs are arrayed together.

• Bitwise Parallelism: Logical operations (AND, OR) execute independently across all 32 slices in parallel.
• Carry Propagation Chain: For addition, carry signals flow sequentially from least significant bit ($bi{t}_0$) to most significant bit ($bi{t}_{31}$), where $CarryOu{t}_i$ connects directly to $CarryI{n}_{i+1}$.

32-Bit ALU Architecture Cascading 32 1-Bit ALU Cells

Signal Interconnections Across Slices

1. Bit Slices $0\dots 31$: Each cell $i$ receives operand bits $a_i$ and $b_i$, producing $Resul{t}_i$.
2. Centralized Control (ALUop): The same ALUop control lines are broadcast to the operation multiplexer of every 1-bit slice simultaneously.
3. Carry Chain:
   • $CarryI{n}_0$ provides the initial carry input to $AL{U}_0$.
   • $CarryOu{t}_i\to CarryI{n}_{i+1}$ for $i\in \{0\dots 30\}$.
   • $CarryOu{t}_{31}$ yields the final overall carry flag for the 32-bit operation.

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Extending the ALU (Subtract & Comparisons)

By adding minimal control logic to the basic 1-bit ALU primitive, the full CPU ALU expands functionality to support:

• Subtraction ($A-B$): Invert $B$ bits (via a 2:1 Mux with a $B_{invert}$ signal) and set initial $CarryI{n}_0=1$ to execute $A+\overline{B}+1$.
• Set Less Than (SLT): Uses subtraction sign-bit evaluation ($A-B<0$) to output $1$ if $A<B$, otherwise $0$.
• Zero Flag ($Zero$): NORs all 32 result bits together ($\overline{R_0+R_1+\cdots +R_{31}}$) to signal branch conditions when $A=B$.

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Related Notes

• Mux & Demux
• Encoder & Decoder
• Adders & Subtractors
• Comparators
• Multiplier & Divider
• Arithmetic Logic Unit