Sequential Circuits

Overview

Unlike combinational networks whose outputs depend solely on present inputs, a Sequential Circuit incorporates memory elements and feedback paths. Its output and next state depend on both current inputs and past outputs (stored state history). Sequential logic enables data storage, execution of sequenced multi-cycle task pipelines, and the physical realization of the Memory Hierarchy—spanning ultra-fast 6-Transistor (6T) SRAM cells and Flip-Flops down to high-density capacitor-based DRAM and non-volatile mass storage.

Fundamentals of Sequential Circuits & Memory

Sequential circuits form the core of digital processing units by maintaining state and controlling operations over time.

• Sequential Logic Function: Output $Y(t)=f(X(t),S(t))$, where $X(t)$ represents current inputs and $S(t)$ represents internal state variables.
• Core Capabilities:
  1. Data Storage: Persists single bits or multi-bit binary words across clock cycles.
  2. Task Sequencing: Executes ordered sequences of operations (e.g., instruction execution, counter stepping).

Memory Hierarchy & RAM Technology Primitives

System memory is structured in a Hierarchy that trades off access latency for density, capacity, and cost per bit.

SRAM

SRAM vs. DRAM Architecture

Submodule Notes

• Latches & Flip-Flops
  Fundamental bistable storage elements: SR Latches, level-sensitive Gated Latches, D Latches, Master-Slave D Flip-Flops, edge-triggering, transistor counts, and reset/preset controls.

• Registers and Counters
  Multi-bit parallel registers, Serial-In/Serial-Out shift registers, sequence pattern recognizers, 4:1 multiplexer-based Universal Shift Registers, and modulo state counters.

• Finite State Machines
  Behavioral controllers, state diagrams, state transition tables, Mealy vs. Moore machines, and the 5-step FSM circuit synthesis process.

• Timing Constraints in Sequential Designs
  Physical timing analysis: contamination ($t_{cd},t_{ccq}$) and propagation ($t_{pd},t_{pcq}$) delays, setup ($t_{\text{setup}}$) and hold ($t_{\text{hold}}$) constraints, hold violation fixes, and worst-case clock skew ($t_{\text{skew}}$).

Related Submodules & Directories

• Arithmetic Logic Units (ALUs)
• Logic Design & K-Maps
• Number Representation & Basic Logic Gates
• Digital Systems
• Computer Systems